1. Field of the Invention
The present invention relates to a fabrication method of a memory. More particularly, the present invention relates to a fabrication method of an non-volatile memory.
2. Description of Related Art
Electrically erasable programmable read-only-memory (EEPROM) is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. Because the stored data will be retained even after power to the device is removed, EEPROM has been broadly applied in personal computer and electronic equipment.
Typically, the floating gate and the control gate of an electrically erasable programmable read-only-memory are fabricated with polysilicon. In programming the memory, the injected charges are evenly distributed in the polysilicon floating gate. However, if the tunneling layer underneath the polysilicon floating gate contains some defects, a leakage current may form leading to a drop in the reliability of the device.
To resolve the above-mentioned problem, an insulating, charge-trapping layer often takes the place of the conventional floating gate in the memory. A material used in forming the charge-trapping layer includes silicon nitride, for example. Since the charge-trapping layer normally includes a silicon oxide layer above and below thereof to form an oxide-nitride-oxide (ONO) stacked structure, this type of memory is often referred as a silicon-oxide-nitride-oxide-silicon (SONOS) memory. In programming a SONOS memory, electrons injected into the silicon nitride layer are not distributed evenly. In other words, most injected electrons are localized in one particular region within the silicon nitride layer. Therefore, not only the leakage current problem is resolved, two bits of data can be stored in a single memory cell to form the so-called 2 bits-per-cell non-volatile memory.
FIG. 1 is a schematic, cross-sectional view diagram of a conventional SONOS memory cell. Referring to FIG. 1, the SONOS memory cell is constructed with a substrate 100, a source region 102, a drain region 104, a lower silicon oxide layer 106, a silicon nitride layer 108, an upper oxide layer 110, and a gate layer 112. The lower silicon oxide layer 106, the silicon nitride layer 108 and the upper oxide layer 110 disposed over the substrate 100 constitute the silicon oxide-silicon nitride-silicon oxide (ONO) stacked layer 114. Further, as shown in FIG. 1, the regions 116 and 118 depict the charge-storing regions. For a SONOS memory cell, charges are injected to the silicon nitride layer near the source region 104 and the drain region 102. In other words, the charge storing regions 116, 118 can each stored with one bit of data, and a 2 bit per cell type of non-volatile memory is provided.
The injected charges are Gaussian distributed in the regions 116 and 118 in the silicon nitride layer 108 (as shown by curves 120 and 122 in FIG. 1). As the integration of device increases and the device dimension gradually decreases, the charge storing regions 116, 118 approaches and even overlaps each other. The bits stored in the regions 116 and 118 will influence each other. As a result, the reliability of the memory is reduced.